    超大規(guī)模集成電路可測(cè)性設(shè)計(jì)(DFT)技術(shù)與實(shí)踐培訓(xùn)

1、DFT overview DFT 概述
What is and Why DFT;
VLSI implementation process;
Manufacturing Defect;
Manufacturing Test;
Automatic Test Equipment (ATE)
introduction
2、Test and fault 測(cè)試和故障
Observability and Controllability
Role of Test
Test Development Flow
Real Tests
DFT Cost
Fault Modeling
3、DFT Methods introduction DFT 方法學(xué)介紹
DFT Methods
Ad Hoc DFT
Scan Basic Concept
MBIST Basic Concept
LBIST Basic Concept
BSCAN Basic Concept
JTAG Architecture
IP Test
4、Mainstream DFT EDA tools and chip DFT
integrated solutions.主流DFT 工具與芯片DFT技術(shù)介紹
DFT Compiler (DC);
Mentor Testkompress/TessentMbist/
TessentBoundary Scan;
Synopsys TetraMAX;
Cadence Modus;
DFT integrated solutions;
5、Scan introduction ( with DFT compiler)芯片scan技術(shù)介紹
Understanding Scan Testing;
Scan Chain Insertion Flow Preview;
Test Protocols and DRC;
Test Ready Compile;
Top Down Scan Insertion Flow;
Bottom Up Scan Insertion Flow;
Scan Compression method
（XOR vs OPMISR）;
Lab DFT Compiler introduce
6、ATPG introduction.芯片ATPG技術(shù)介紹
What is testing and ATPG
Stuck at ATPG
Transition ATPG
Path delay ATPG
IDDQ ATPG
D algorithm
7、ATPG implementation ( with TestKompress/
TetraMAX Lab). 芯片ATPG技術(shù)實(shí)現(xiàn)
ATPG Flow Preview
Building Design
Design Rules Check
Controlling ATPG
Saving Pattern and Pattern Validation
Lab TestKompress/TetraMAX introduce
8、Understanding MBIST
芯片MBIST技術(shù)介紹
Why Memory testing is required?
Memory Faults
Memory Testing Techniques
Memory BIST algorithms
Memory interface test (RAM Sequential
Test)
9、MBIST Implement ( with Tessent MBIST Lab). 芯片MBIST技術(shù)實(shí)現(xiàn)
Tessent MBIST generation and insertion
flow;
ETChecker Introduction;
Block Flow Planning with ETPlanner;
ETAssemble and ETSignoff in the Block
Flow;
Memory BIST Hierarchical Top Level Flow;
MBIST Diagnostics;
Tessent MBIST parameters setting;
Lab Tessent MBIST introduce;
10、DFT latest innovative technologies. 新的DFT技術(shù)介紹
Channel Sharing of scan
Cell aware ATPG technique
ATPG Hierarchy scan technique
Logic BIST/SCAN Hybrid technique
Physical aware scan insertion
2.5D/3D Test
IJTAG（IEEE 1687）
Partial Good Test
11、DFT Flow and tools. 芯片項(xiàng)目中的DFT 流程和工具
DFT engineer 5 tasks
DFT flow (top and block level)
DFT flow inputs/outputs in each step
DFT tools (flow used)
12、DFT SPEC and Checklist. 芯片項(xiàng)目中的DFT規(guī)格書和檢查表
DFT spec of one chip
DFT check-list in project
DFT patterns check-list
13、Frequently see DFT problems (DFT
architecture). 工程實(shí)踐中的DFT常見問題（架構(gòu)方案）
Consider the three keys for DFT - Test
costs/quality/yield;
Define the whole chip DFT SPEC and test
plan ;
Implement Low-power scan inserting;
Implement Low-power MBIST;
Implement Low-power ATPG;
14、Frequently see DFT problems （Design and
debug. 工程實(shí)踐中的DFT常見問題（電路設(shè)計(jì)和調(diào)試）
Tessent MBIST debug skills;
Improve the scan test coverage;
Insert test points;
Insert On-Chip Clock Control;
Deliver the DFT related SDC files for timing;
DFT timing issue debug;
Debug the mismatches in scan/mbist
/bscan simulation
15、Frequently see DFT problems （ATE test）.工程實(shí)踐中的DFT常見問題 （ATE測(cè)試）
Troubleshooting Test Patterns
ATE patterns fail - debug
Scan diagnose flow
Fault analysis
Improve the yield
16、DFT Summary. DFT小結(jié)
The history and DFT
The current situation of DFT
The future of DFT
DFT EDA tools – compare and evaluate
Thinking Design in DFT
How to be a good DFT engineer
The course summary